1. Field of the Invention
This invention pertains to semiconductor digital circuits, and more particularly, to a branch or field thereof known as current controlled gates, which are bipolar logic circuits intended for use on dense, very large scale integrated circuit gate arrays. In this particular field of current controlled gate circuits, the emphasis is upon extending the art to ever greater densities and to the achievement of lower propagation delays.
2. Background Information
In order to provide background information so that the invention may be completely understood and appreciated in its proper context, reference may be made to a number of prior art patents and publications as follows:
U.S. Pat. Nos. 2,964,652; 3,505,535; and 4,092,551; all of which are assigned to the assignee of the present invention; Article in IBM Technical Disclosure Bulletin Vol. 24 No. 6, pages 3031-3034, November 1981, entitled "Current Controlled Gate Push-Pull Dotting"; U.S. patent application Ser. No. 221,684 filed Dec. 30, 1980, and assigned to the assignee of the present invention.
U.S. Pat. No. 3,505,535 to Cavaliere in particular discloses an improvement on what has come to be known in the art as the "current switch", a form of circuitry first disclosed in U.S. Pat. No. 2,964,652 to H. S. Yourke. In the current switch a constant current is switched either to one or more logic input transistors, or to a grounded-base transistor, depending upon potential levels of the logic signals at the bases of the input transistors in relation to the reference potential at the grounded base transistor. Because the current which flows through the collector load resistors is constant and predetermined, circuit parameters may be selected so as to limit the potential swing of the collectors, thereby to maintain the transistors out of saturation. Nevertheless, despite the useful applications of the current switch, per se, U.S. Pat. No. 3,505,535 provides an improved clamp for the basic circuit, thereby to insure that the transistors therein are prevented from going deeply into the saturation region. This is achieved by a non-linear load impedance network in the form of a transistor at the output of the logic input transistors.
U.S. Pat. No. 4,092,551 to Howard et al discloses a so-called "speed-up" circuit, which uses a base-collector junction as a capacitor in order to aid in discharging the base of a saturated transistor; however, the present invention distinguishes therefrom as will be made apparent in the later description.
The article cited which appeared in the IBM Technical Disclosure Bulletin for November 1981 discloses a current controlled gate circuit which includes a Schottky barrier diode, connected between the emitter of one output transistor and the collector of the other. However, that circuit is directed to solving the difficult problem associated with the "dotting" of push-pull outputs, and the form and function of the circuit is similar to U.S. patent application Ser. No. 221,684 cited above.
Another disclosure which furnishes background information is that above cited U.S. patent application Ser. No. 221,684 in the name of J. A. Dorler et al, which discloses a transient controlled current switch in several forms or embodiments. However, that circuit does not operate in the manner provided by the present invention.
Whatever the precise merits, features and advantages of the above cited references, none of them achieves or fulfills the purposes of the current controlled gate circuit of the present invention.
Accordingly, it is a principal object of the present invention to achieve very low power dissipation in the operation of a current controlled gate circuit.
It is another principal object of the present invention to provide a circuit with characteristics that will enable the achievement of greater density in large scale gate arrays, as well as the achievement of lower propagation delays.
It should be noted that in the description of the circuit of the present invention it may appear that the topology is quite complex and, therefore, this might seem inconsistent with the circuit being used for a dense "master slice". However, density in gate arrays is actually limited by the space required to interconnect the gates and therefore, the space that the silicon devices occupy becomes irrelevant as long as they fit into a rectangle prescribed by the required wiring channels per gate in the two levels above the gate dedicated to interconnection metal.
In any event, it will be clear that to advance the art it is necessary that a logic circuit have minimal propagation delay. This propagation delay may be thought of as being composed of two parts: the unloaded delay, and the added delay due to loading (e.g. fan out, wiring capacitance, etc.). The delay per unit load is called the sensitivity due to loading (for example: 0.1 ns/pf or 0.3 ns/fo, where ns is nanoseconds, pf is picofarads and fo is fan out).